Analog Backend System
There are two synthesizers in the LO Synthesizer system namely as SYNTH1 and SYNTH2. SYNTH1 uses three VCO's and the SYNTH2 uses YTO. Each Oscillator is preceeded by its own differential OP-AMP active loop integrator filter with a circuit optimized for the range of oscillator. An oscillator is selected depending on the frequency to be synthesized and its output is routed to the input of Power Amplifier through a single-pole four-throw switch. It is ensured that the output of the switch is typically +5dBm over the full range of the synthesizer.
The synthesizers SYNTH1 and SYNTH2 accept a reference signal of 105MHz from a Voltage Controlled Crystal Oscillator(VCXO), which is a part of the narrow band Offset Phase Lock Loop in the scheme for Local Oscillator Reference (LOR) Generation. The fifth overtone crystal is used in the circuit of VCXO and provides a gain of about 200Hz/volt. The loop bandwidth is typically about 40Hz. The synthesizer also accepts offset signal at 1MHz which is regenerated in the LOR system at each antenna with an edge jitter of less than 2 ns.
The frequency of reference and VCXO signals are divided into a value equal to step size using synchronous up-counters and dual-modulus pre-scalars using Pulse Swallow Techniques. A high gain (about 300mV/radian) digital Phase-Frequency detector compares the two divided signals and produces a pulse width modulated waveform at the output, whose DC average is proportional to the phase difference between the input waveforms. The error signal is integrated in a loop filter and drives the oscillator in a proper direction so as to achieve and maintain lock.
The 1MHz signal is used for the purpose of synchronization. If the system is operating at a step size of S MHz and relocks at a frequency FLO after a period of unlock (caused by whatever reason), the phase of the relocked signal could jump by (2* PI* X* FLO) degrees, with a variable X free to take any integer value from 0 to 100/S. This is because there is no retention of "prior" condition in the event of a disturbance. The synchronization scheme aims to prevent this by giving a "time stamp" to the divider chain.