The Four Input Card ( FIC ) combines four dish inputs. There are eight such cards to handle the 30 dish signals. The basic functions of these cards are :
a.Accepts the complex spectral voltages from FFT modules ( coming from 4 dishes x 2 Polarizations ).
b.Converts the complex voltages into Power ( 6-bits ). Real, Imaginary terms ( 5, 5-bit ) after adjusting for the expected input signal range.
c.Combines the 4-dish Power, Real-Imaginary Terms.
Hardware Details:
The spectral voltage outputs from the FFT system enters ECL to TTL converters and are converted to the TTL levels. These signals are latched using the tri-statable input registers ( 74FCT162374 SMD ). The register outputs are tri-stated for the diagnostic operations. The mode control register ( M0 bit ) has to be programmed for this purpose. During the diagnostic mode it is possible to tri-state the input register and feed a common 12-bit number from a programmable register to the IPC inputs. It consists of two numbers of 128K x 8 EPROMs ( CY27H010 ) per dish input. There are four such sets of EPROMs in the Four Input Cards. The IPC stage produces the Power ( 6-bits ), Real ( 5-bits ) & Imaginary ( 5-bits ). The first EPROM ( for example U16 ) outputs the power ( 6-bits ) and the 2 LSBs of the real part. The second EPROM ( U17 ) outputs the remaining 3-bits of real part and the 5-bits of imaginary part.
The EPROM ( IPC stage ) gets the expected input signal range information from the Gain RAMs. For this purpose the upper four address bits ( A12 to A15 ) of the EPROMs are used to select one out of the 16 possible 4K size tables. These tables contain the optimum look-up outputs corresponding to the different input ranges. During the operation of the system, gain corrections are accomplished by suitably changing to an expected table for every channel of the spectral inputs. The details about the gain tables to be used ( 4-bit wide data ) are coming from Read / Write RAMs ( CY7C150 ). There are 4 such RAMs in each cards corresponding to the 4 dish inputs. The gain values corresponding to 4 dish inputs. The gain values corresponding to 256 spectral channels and for the 2 polarisations for the four dishes are stored in these RAMs. Using these RAMs it is possible to store upto 512 range values ( synchronisation to be adjusted ) per polarisation. The RAM location are pre-loaded during the set-up operation. The RAMs are addressd by a 10-bit channel counter. The channel counter is implemented inside an EPLD ( EMP5032 ). This counter operates in synchronisation with the FFT system. When a speecific channel data from FFT arrives at the IPC stage inputs, the corresponding RAM locations are accessed and the stored range values are supplied to the IPC lookups. The odd and the even numbered sets of location in the two polarisation channels. The synchronisation signal ( XINIT ) is derived from the clock sequence EPROM ( CY7C245A ) located in the Clock-Controller Card. The control computer loads two Gain RAMs are loaded together. After loading, the computer can read back and verify the operation. The integrity of the data stored in the RAMs is checked using the pre-computer parity bits stored in a parity RAM. The parity RAM is also addressed by the channel counter, hence the parity errors are checked automatically when each time a new location is accessed. The contents of the parity RAM can also be read by the control computer for verification, if required.
The output data from the IPC stage enters the binary summing network. At first the power, real and imaginary terms are latched in the clearable registers ( 74FCT162823 SMD ). The 'clear signals' are taken from the antenna mask register ( U60 ). The mask register can be programmed to execute any combinations of the dishes in the summing. As already mentioned, seperate masking provision are available for power, and real-imaginary ( IA mask, PA mask ) summing networks.
1.First Level Addition ( Dual 6-bits plus 6-bits adders ):
After the clearable register, the data enters the Level-1 summing stage of the binary network. At this stage succesive two inputs are added together. The adders are implemented using EPROMs ( CY7C264 ). These EPROMs take in two 6-bit inputs, adds them and produces a 7-bit sum output. in the case of real, imaginary terms the inputs are only 5-bit wide, hence the most significant bits ( MSB ) are tied to ground at the clearable register inputs while the same 6-bit adders are used for summing. The real, imaginary term network adders ignore these MSBs. Then the sums produced are stored and forwarded to the next pipeline stage using a latch ( 74FCT162374 SMD).
2.Second Level Addition ( 7-bit plus 7-bits adder ):
The second level of summing produces the output corresponding to the four input sum. The power term will be 8-bit wide, the real and imaginary are 7-bit each. These 7-bit adders are implemented again using EPROMs ( CY7C276 ). All the three sums ( power, real-imaginary terms ) are further latched and forwarded to the 'Eight Input Cards' through the backplane.
In the 4-input cards, a provision ia available to adjust the phase delays for the clock and the Init pulse so as to meet the proper timing synchronisation. The parity error status is displayed using LEDs and also available to the control computer as a status flag. The IA and PA mask values are displayed on the front panel. An EPLD based decoder circuitry is used for selectively writing and reading the programmable registers and the Gain RAMs present in the card. The input conversion stage has a provision to switch to a second bank for any diagnostic purpose. This is accomplished by programming the Bank selection bits in the mode control register. The gain RAMs are loaded from the control computer by tri-stating a 10-bit latch that is feeding the channel counter outputs to teh RAMs address lines. The RAM address values are supplied from the control computer while loading and reading the contents. The tri-state control is achieved by setting a ( MI ) bit in the mode control register. These are general purpose lines provided in the board between the EPLDs and teh backplane euro connector to accommodate any future requirements. A 1:10 ow-skew FCT clock driver ( 74FCT807 SMD ) is used to distribute the clock to the different sections of te four input card. There are 4 pipeline stages in this card.
All the 8 first cards simultaneously receive te synchronisation signal through the backplane.